This invention relates to a voltage converting circuit which outputs an intermediate level of power supply voltage and particularly to a voltage converting circuit which is suitable for use in a MIS type integrated circuit.
It is often required in a MIS type integrated circuit to use a constant voltage having an intermediate level with respect to the power supply voltage supplied from an external circuit. For instance, an intermediate level of, for example, 2.5 V is steadily applied to a common capacitor electrode incorporated into memory cells in a MIS type dynamic random access memory operative under a power supply voltage of 5 V.
The intermediate level is obtained easily using a resistance dividing circuit as shown on FIG. 1. In this figure, resistors R.sub.1, R.sub.2 divide the power supply voltage V.sub.cc in order to obtain an intermediate voltage V.sub.cc ' to be provided to a load circuit L. For a sufficiently low load current, when R.sub.1 =R.sub.2, then V.sub.cc '=V.sub.cc /2. However, when a load circuit L consumes a current that is sufficiently high, such a relation is not maintained. Moreover, in this example, the resistors R.sub.1, R.sub.2 are connected in series between the power source V.sub.cc of +5 V and the power source V.sub.ss of 0 V, a current always flows from V.sub.cc to V.sub.ss, and thereby a large amount of power is consumed. This is one disadvantage of this circuit. Such power consumption can be reduced by making large the resistors R.sub.1, R.sub.2. However, if a resistance value is large, the above change in the voltage V.sub.cc ' at node N1 due to a load current becomes large.
The circuit shown in FIG. 2 is effective for reducing power consumption and fluctuation of the load voltage V.sub.cc ' due to a change of the load current. In this circuit, a divided voltage of power source V.sub.cc obtained through the resistors R.sub.1, R.sub.2 is given to the gate of a MIS transistor Q.sub.1 and an output of said transistor Q.sub.1 is applied to the load circuit L. Q.sub.1 constitutes an output transistor of low output impedance. Therefore, a load current flows through the drain and source of transistor Q.sub.1 but does not flow into the voltage dividing circuit R.sub.1, R.sub.2. There is no change of load voltage V.sub.cc ' and, since the dividing circuit only gives a voltage to the gate of the MIS transistor Q.sub.1, the circuit is allowed to have a high resistance value, thus resulting in less power consumption. Because of the relation V.sub.N -V.sub.th =V.sub.cc ' between the voltage V.sub.N of node N.sub.1 and load voltage V.sub.cc ' , when V.sub.cc '=V.sub.cc /2 is required, V.sub.N is selected to have a value satisfying the relation, V.sub.N =V.sub.th +V.sub.cc /2. V.sub.th indicates the gate threshold voltage of the MIS transistor Q.sub.1.
However, this circuit has a problem in that a threshold voltage V.sub.th of the transistor Q.sub.1 directly affects a load voltage V.sub.cc ' and V.sub.th changes in accordance with the integration circuit manufacturing process, whereby the load voltage V.sub.cc ' fluctuates for each product.
Namely, it is well known that a resistance ratio of two resistors in an integrated circuit has only a small error, although there are changes of V.sub.th depending on the manufacturing process. For example, it is easy to ensure that an error of resistance value ratio is as small as 1% or less. Therefore, a voltage V.sub.N of node N.sub.1 can be set accurately. Meanwhile, the gate threshold voltage of a MIS transistor is easily affected by a process fluctuation, and an error as small as 0.2 V can easily be generated. This error means, for example, that an error of about 10% easily occurs in the circuit for generating an output voltage V.sub.cc ' of 2.5 V.